module MTrigger(
    input               clk50M,
    input               rst_n,
    input       [1:0]   TriggerMode,
    output              VT_st,
    input               LAN,
    input       [3:0]   TriggerDNum,

    input               CH0_TR_OUT,
    input               CH1_TR_OUT,
    input               CH2_TR_OUT,
    input               CH3_TR_OUT,

    output              CH0_TR_IN,
    output              CH1_TR_IN,
    output              CH2_TR_IN,
    output              CH3_TR_IN,

    input               CH0_DRange_gt,
    input               CH1_DRange_gt,
    input               CH2_DRange_gt,
    input               CH3_DRange_gt,

    output  reg         CH0_TriggerST,
    output  reg         CH1_TriggerST,
    output  reg         CH2_TriggerST,
    output  reg         CH3_TriggerST,

    input               TRIGGERINF      //
);


// reg lan_aft,trgin_aft,ch0_aft,ch1_aft,ch2_aft,ch3_aft;
// reg lan_pre,trgin_pre,ch0_pre,ch1_pre,ch2_pre,ch3_pre;
// wire lan_jr,trgin_jr,ch0_jr,ch1_jr,ch2_jr,ch3_jr;
// assign lan_jr   = (!lan_pre     ) && lan_aft;
// assign trgin_jr = (!trgin_pre   ) && trgin_aft;
// assign ch0_jr   = (!ch0_pre     ) && ch0_aft;
// assign ch1_jr   = (!ch1_pre     ) && ch1_aft;
// assign ch2_jr   = (!ch2_pre     ) && ch2_aft;
// assign ch3_jr   = (!ch3_pre     ) && ch3_aft;

// always @(posedge clk50M or negedge rst_n) begin
//     if (!rst_n) begin
//         {lan_pre,lan_aft}       <= 2'b00;
//         {ch0_pre,ch0_aft}       <= 2'b00;
//         {ch1_pre,ch1_aft}       <= 2'b00;
//         {ch2_pre,ch2_aft}       <= 2'b00;
//         {ch3_pre,ch3_aft}       <= 2'b00;
//         {trgin_pre,trgin_aft}   <= 2'b00;
//     end else begin
//         {lan_pre,lan_aft}       <= {lan_aft,LAN};
//         {ch0_pre,ch0_aft}       <= {ch0_aft,CH0_TR_OUT};
//         {ch1_pre,ch1_aft}       <= {ch1_aft,CH1_TR_OUT};
//         {ch2_pre,ch2_aft}       <= {ch2_aft,CH2_TR_OUT};
//         {ch3_pre,ch3_aft}       <= {ch3_aft,CH3_TR_OUT};
//         {trgin_pre,trgin_aft}   <= {trgin_aft,TRIGGERINF};
//     end
// end

// always @(posedge clk50M or negedge rst_n) begin
//     if (!rst_n) begin
//         CH0_TR_IN   <= 1'b0;
//         CH1_TR_IN   <= 1'b0;
//         CH2_TR_IN   <= 1'b0;
//         CH3_TR_IN   <= 1'b0;
//         VT_st       <= 1'b0;
//     end else begin
//         case (TriggerMode)
//             2'h1: begin     //消息触发
//                 if ((lan_jr == 1'b1) && (VT_DRange_gt == 1'b1)) begin
//                     CH0_TR_IN   <= 1'b1;
//                     CH1_TR_IN   <= 1'b1;
//                     CH2_TR_IN   <= 1'b1;
//                     CH3_TR_IN   <= 1'b1;
//                     VT_st       <= 1'b1;
//                 end else begin
//                     CH0_TR_IN   <= 1'b0;
//                     CH1_TR_IN   <= 1'b0;
//                     CH2_TR_IN   <= 1'b0;
//                     CH3_TR_IN   <= 1'b0;
//                     // VT_st       <= 1'b0;
//                 end
//             end
//             2'h2: begin     //信号触发
//                 if (ch0_jr && TriggerDNum[0]) begin
//                     CH0_TR_IN   <= 1'b1;
//                     CH1_TR_IN   <= 1'b1;
//                     CH2_TR_IN   <= 1'b1;
//                     CH3_TR_IN   <= 1'b1;
//                     VT_st       <= 1'b1;
//                 end else if (ch1_jr && TriggerDNum[1]) begin
//                     CH0_TR_IN   <= 1'b1;
//                     CH1_TR_IN   <= 1'b1;
//                     CH2_TR_IN   <= 1'b1;
//                     CH3_TR_IN   <= 1'b1;
//                     VT_st       <= 1'b1;
//                 end else if (ch2_jr && TriggerDNum[2]) begin
//                     CH0_TR_IN   <= 1'b1;
//                     CH1_TR_IN   <= 1'b1;
//                     CH2_TR_IN   <= 1'b1;
//                     CH3_TR_IN   <= 1'b1;
//                     VT_st       <= 1'b1;
//                 end else if (ch3_jr && TriggerDNum[3]) begin
//                     CH0_TR_IN   <= 1'b1;
//                     CH1_TR_IN   <= 1'b1;
//                     CH2_TR_IN   <= 1'b1;
//                     CH3_TR_IN   <= 1'b1;
//                     VT_st       <= 1'b1;
//                 end else begin
//                     CH0_TR_IN   <= 1'b0;
//                     CH1_TR_IN   <= 1'b0;
//                     CH2_TR_IN   <= 1'b0;
//                     CH3_TR_IN   <= 1'b0;
//                     // VT_st       <= 1'b0;
//                 end
//             end
//             2'h3: begin
//                 if ((trgin_jr == 1'b1) && (VT_DRange_gt == 1'b1)) begin
//                     CH0_TR_IN   <= 1'b1;
//                     CH1_TR_IN   <= 1'b1;
//                     CH2_TR_IN   <= 1'b1;
//                     CH3_TR_IN   <= 1'b1;
//                     VT_st       <= 1'b1;
//                 end else begin
//                     CH0_TR_IN   <= CH0_TR_IN;
//                     CH1_TR_IN   <= CH1_TR_IN;
//                     CH2_TR_IN   <= CH2_TR_IN;
//                     CH3_TR_IN   <= CH3_TR_IN;
//                     // VT_st       <= 1'b0;
//                 end
//             end
//             default: ;
//         endcase
//     end
// end

assign VT_st = ch_trig_in;
assign CH0_TR_IN = ch_trig_in;
assign CH1_TR_IN = ch_trig_in;
assign CH2_TR_IN = ch_trig_in;
assign CH3_TR_IN = ch_trig_in;

wire ch_trig_in;
assign ch_trig_in = (TriggerMode == 2'h1) ? lan_trig_in :
                    (TriggerMode == 2'h2) ? (ch0_trig_in || ch1_trig_in || ch2_trig_in || ch3_trig_in) :
                    (TriggerMode == 2'h3) ? ext_trig_in : 1'b0;

//external trigger
reg ext_trig_in;
always @(posedge TRIGGERINF or negedge rst_n) begin
    if (!rst_n) begin
        ext_trig_in   <= 1'b0;
    end else begin
        if (VT_DRange_gt == 1'b1) begin
            ext_trig_in   <= 1'b1;
        end else begin
            ext_trig_in   <= 1'b0;
        end
    end
end

//force trigger
reg lan_trig_in;
always @(posedge LAN or negedge rst_n) begin
    if (!rst_n) begin
        lan_trig_in <= 1'b0;
    end else begin
        if (VT_DRange_gt == 1'b1) begin
            lan_trig_in <= 1'b1;
        end else begin
            lan_trig_in <= 1'b0;
        end
    end
end

reg ch0_trig_in;
always @(posedge CH0_TR_OUT or negedge rst_n) begin
    if (!rst_n) begin
        ch0_trig_in <= 1'b0;
    end else begin
        if (TriggerDNum[0] == 1'b1) begin
            ch0_trig_in <= 1'b1;
        end else begin
            ch0_trig_in <= 1'b0;
        end
    end
end

reg ch1_trig_in;
always @(posedge CH1_TR_OUT or negedge rst_n) begin
    if (!rst_n) begin
        ch1_trig_in <= 1'b0;
    end else begin
        if (TriggerDNum[1] == 1'b1) begin
            ch1_trig_in <= 1'b1;
        end else begin
            ch1_trig_in <= 1'b0;
        end
    end
end

reg ch2_trig_in;
always @(posedge CH2_TR_OUT or negedge rst_n) begin
    if (!rst_n) begin
        ch2_trig_in <= 1'b0;
    end else begin
        if (TriggerDNum[2] == 1'b1) begin
            ch2_trig_in <= 1'b1;
        end else begin
            ch2_trig_in <= 1'b0;
        end
    end
end

reg ch3_trig_in;
always @(posedge CH3_TR_OUT or negedge rst_n) begin
    if (!rst_n) begin
        ch3_trig_in <= 1'b0;
    end else begin
        if (TriggerDNum[3] == 1'b1) begin
            ch3_trig_in <= 1'b1;
        end else begin
            ch3_trig_in <= 1'b0;
        end
    end
end

reg VT_DRange_gt;
always @(posedge clk50M or negedge rst_n) begin
    if (!rst_n) begin
        CH0_TriggerST   <= 1'b0;
        CH1_TriggerST   <= 1'b0;
        CH2_TriggerST   <= 1'b0;
        CH3_TriggerST   <= 1'b0;
        VT_DRange_gt    <= 1'b0;
    end else begin
        if (CH0_DRange_gt && CH1_DRange_gt && CH2_DRange_gt && CH3_DRange_gt) begin
            CH0_TriggerST   <= 1'b1;
            CH1_TriggerST   <= 1'b1;
            CH2_TriggerST   <= 1'b1;
            CH3_TriggerST   <= 1'b1;
            VT_DRange_gt    <= 1'b1;
        end else begin
            CH0_TriggerST   <= 1'b0;
            CH1_TriggerST   <= 1'b0;
            CH2_TriggerST   <= 1'b0;
            CH3_TriggerST   <= 1'b0;
            VT_DRange_gt    <= 1'b0;
        end
    end
end


endmodule
